Andes Tech and Spacetouch Team up to Unveil High Tech Edge-Side AI
CIOTechOutlook Team | Tuesday, 09 January 2024, 05:55 IST

Andes Technology's D25F processor, based on the AndeStar™ V5 architecture, is a 32-bit RISC-V CPU IP core equipped with P-extension (DSP/SIMD extension, draft version). Combined with the RISC-V DSP/SIMD ISA compiler, DSP library and emulator, alongside the highly optimized AndeSoft™ NN Library, customers can efficiently accelerate AI application computing, as per Andes Technology.
The D25F can be configured as an AXI 64-bit or AHB 64/32-bit bus interface, including an external connection for direct access to local memory. It can also be outfitted with a Platform Level Interrupt Controller (PLIC), which supports over 1,000 interrupt sources and enables fast interrupt response, prioritization, and preemption. The Andes Custom Extension™ (ACE) offers customized special-purpose instructions for even more versatility.
"With the longstanding cooperation between Spacetouch and Andes Technology, our SoCs are equipped with AndesCore™ processors that offer powerful performance with multiple optional features to us.” Hu Yingzhe, CEO of Spacetouch, remarked. "The combination of the D25F RISC-V processor and Spacetouch’s heterogeneous multi-core AI audio processor IC brings more innovation and possibilities to the fields of audio processing, embedded systems and mobile devices. With the processor IP and technical support provided by Andes Technology, the two companies have a good basis to form more successful cooperation in the future. “
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